Vehicles and specifically cars or trucks may be equipped with one or more cameras. The camera is connected to an electric control unit (ECU) for processing of the video data. Such camera-ECU may be of the LVDS (Low Voltage Differential Signaling) type.
Furthermore, the video data from the camera may be transmitted to the ECU by a cable of the PoC (Power over Coax) or STP (Single Twisted Pair) type. Thus, the video data from the camera are transmitted serially to the ECU. This requires a serializer on the camera side and a deserializer on the ECU side.
In the existing LVDS type of camera-ECU systems the number of GPIOs (General Purpose Input/Output) available in the SerDes (Serializer-Deserializer) chip set is limited. Typically, SerDes chip sets have up to 4 GPIOs. As per supplier road map the number will remain the same due to the package, the silicon chip properties and/or cost factors.
Having a limited number of GPIOs available between the camera and the ECU introduces design restrictions. Specifically, due to the advanced designs, lower sizes of cameras are required for simple mountings which imply that many features/functions are controlled, managed or monitored. Eventually the cameras fully become a slave (no MCU (Micro Controller Unit) on camera) and are controlled or monitored by an ECU as the master. These architectural changes require more feature sets especially on the SerDes chip sets, and one such requirement is the increased need of available GPIOs. But as highlighted, the suppliers usually provide limited GPIOs.
The camera system of FIG. 1 shows a camera unit 1 which is connected to a control unit 2, herein also called ECU. Both units 1 and 2 may be connected via a serial connection 3. The camera unit 1 may include a video sensor not shown in FIG. 1. The video sensor provides a parallel video signal via parallel data lines D[x:0], which means a plurality of single data lines D[0], D[1], D[2], . . . , D[x]. The respective video signal is input to a serializer 4 of the camera unit 1. The serializer 4 has respective input bins (also called data contacts) D0, D1, D2, . . . , Dx. Furthermore, the serializer includes an input HSYNC for a horizontal synchronization signal HS, an input VSYNC for a vertical synchronization signal VS and an input PCLKIN for a pixel clock signal PCLK.
Additionally, the serializer 4 has four general purpose input/output pins GPIO0, GPIO1, GPIO2 and GPIO3. Thus, the serializer 4 can receive video data and optionally synchronization signals and a clock as well as other control signals via the GPIOs. The serializer 4 processes these signals to a serial signal transmittable via the serial connection 3 to the control unit 2.
The control unit 2 includes a deserializer 5 to deserialize the serial signal received from the camera unit 1. Therefore, the deserializer 5 has a plurality of data pins or contacts D0, . . . , Dx. Furthermore, the deserializer 5 has outputs HSYNC, VSYNC and PCLK as well as four GPIOs in the present case. The desirializer 5 delivers signals/data to a video processor 6 and/or a micro control unit 7. Therefore, the video processor 6 has a corresponding number of data pins/data contacts D0 to Dx for receiving the data signals from data lines D[0], D[1], . . . , D[x] from the deserializer 5. Furthermore, the video processor 6 has respective dedicated GPIOs (four in the present case) in order to receive respective signals from the GPIOs of the deserializer 5. For the sake of clarity input pins for the horizontal synchronization signal HS, the vertical synchronization signal VS and the pixel clock PCLK from the deserializer 5 are not shown in the diagram of the video processor 6.
The micro control unit 7 also has several dedicated GPIOs. In the example of FIG. 1 the micro control unit 7 has four GPIOs for exchanging signals with the respective GPIOs of the deserializer 5. One GPIO of the micro control unit 7 is not used in the present example.
The limited number of GPIOs available between the video processor 6 and the micro control unit 7 on the one hand and the deserializer 5 on the other hand introduces design restrictions. Therefore, according to the present invention it is proposed to increase the number of monitored I/Os in the overall design by using unused digital parallel video pins on the SerDes chip set. Thus, not only the dedicated, i.e. the specifically intended GPIOs can be used by either the video processor 6 or the micro control unit 7.